In recent years, with the demand for miniaturization of electronic instruments and devices, attempts are being made to miniaturize and densify semiconductor devices used in the electronic instruments and devices. Accordingly, semiconductor devices having a chip-scale package (CSP) structure, in which the miniaturization has been achieved by making the shape of a semiconductor device as close as possible to the shape of a semiconductor element (semiconductor chip), have been developed and fabricated.
In a typical semiconductor device having a CSP structure, a passivation film (insulating film) as a protective film is formed on the surface on a side of a semiconductor wafer where devices are formed, and a reroute layer (reroute pattern) for linking a wiring layer (electrode pads) of each device to the outside of a package through via holes formed at predetermined positions in the insulating film is formed on the insulating film. Further, metal posts are provided on terminal formation portions of the reroute layer, and the entire surface of the side where the metal posts are formed is sealed with sealing resin (except that the top portions of the metal posts are exposed). Furthermore, metal bumps as external connection terminals are bonded to the top portions of the metal posts.
For various kinds of devices including flash memories, DRAMs, and the like, to which semiconductor devices having the relevant CSP structure are applied, the future trend is that the demand for thinning of wafer-level packages in a stage before being divided into individual semiconductor chips is still more increasing. Therefore, a process of grinding the back surface of a wafer is generally performed in order to attempt the thinning.
In a conventional wafer-level package manufacturing process, a process of grinding the back surface of a wafer is performed in the initial stage. Namely, the wafer is thinned by a back grinding (BG) process of a typical method using a wafer back grinding machine, in a stage after a plurality of devices have been formed in the semiconductor wafer (i.e., in a stage before a passivation film (insulating film) is formed on the wafer surface), and then the subsequent steps are performed.
In a process relating to a wafer back grinding process, when the back grinding is performed, a tape for protecting a pattern surface (for convenience, hereinafter, such a tape will be referred to as a “BG tape”) is attached thereto. Here, the back grinding required a dedicated laminator for attaching the BG tape thereto, a dedicated remover for stripping off the BG tape after the wafer back grinding, and further, a stripping tape when the BG tape is stripped off. The BG tape used in the back grinding has the function of planarizing the surface of the side where a pattern is formed, as well as the function of protecting the pattern surface. Accordingly, as the BG tape, a tape of a thick-film type which can accommodate irregularities of the surface is generally used.
Technologies relating to the back grinding process for thinning a wafer as described above include, for example, one in which a wafer back surface is ground after resin sealing (as examples, refer to Patent Documents 1 and 2).
Patent Document 1: Japanese Unexamined Patent Publication No. 2002-270720, and
Patent Document 2: Japanese Unexamined Patent Publication No. 2002-231854.
As described above, in the conventional wafer-level package manufacturing steps, a BG tape of a thick-film type is needed in a process relating to a wafer back grinding. The BG tape of the thick-film type is very expensive. In addition, a dedicated laminator and a dedicated remover (including a stripping tape) are also essential. Accordingly, there is a serious obstacle in terms of cost (increase in manufacturing cost) in realizing the thinning of a wafer-level package
Moreover, in the wafer-level package manufacturing process, the wafer back grinding process is performed in the initial stage, and all subsequent steps need to be performed in a state where a wafer is thin (thin-wafer state). Accordingly, there is a high possibility in that a fatal defect of so-called “wafer cracking” will occur during the process.
In order to cope with the defect, for example, it is possible to conceive of refining a holding and carrying mechanism of a device carrier system so that a thin wafer can be handled in such a state that the wafer cracking does not occur. In that case, however, there is a problem in that the cost relating to the device carrier system increases. Additionally, as another method of avoiding the wafer cracking caused by a process in a thin-wafer state, it is possible to conceive of performing a wafer back grinding process in a stage as close as possible to the end (ideally, in the final stages) in a wafer-level package manufacturing process. For example, if a wafer-back grinding process is performed after resin sealing has been performed in an assembly process in the final stage, at least the wafer cracking caused by a process in a thin-wafer state can be avoided.
However, if a wafer-back grinding process is performed after resin sealing, there is a possibility in that wafer cracking due to another cause may occur. Namely, when resin sealing is performed, for example, as shown in FIG. 10A, molding resin (19) is diffused to the peripheral portion of a wafer (30); the diffused molding resin overflows to a wafer edge portion to reach the wafer back surface (i.e., an overflow of the molding resin to the wafer back surface occurs); accordingly, if a wafer back grinding process is performed in such a state as described above, the resin enters a grinding stone whereby only wafer material (silicon) should be essentially ground, to cause clogging; thus, smooth grinding is hindered; and in some cases, there is a risk in that the wafer may crack. Therefore, unless some skills are applied to the process, it is not appropriate to perform a wafer back grinding process after resin sealing.
Further, a later stage which is conceivable as to be the stage for performing a wafer back grinding process is the stage after solder balls have been mounted and reflow has been performed (after the bonding of solder bumps). However, even in this stage, the molding resin is left overflowed to the wafer back surface. Further, an expensive BG tape, a dedicated laminator, and a dedicated remover (including a stripping tape) remain needed. The problem of the increase in the manufacturing cost is left unsolved.
Moreover, there is also a problem in that, when a wafer is thinned, the entire wafer warps during the manufacturing process. For example, when sealing with and a thermal cure of molding resin are performed, a very thin wafer is pulled toward the resin layer side under the influence of the thermal shrinkage of the sealing resin, and the entire wafer warps. Accordingly, processes (solder ball mounting, reflow, dicing, and the like) after the resin sealing step must be performed in the state where the wafer is warped. As described above, conventional technologies have a disadvantage in that, when a wafer-level package is thinned, the entire wafer warps.
As a method of coping with such a disadvantage, it is possible to conceive of, for example, forming a film layer (e.g., an insulating resin film made of epoxy resin, silicone resin, polyimide resin, or the like) for warping correction, on the wafer back surface by vacuum lamination. In this case, an epoxy-, silicone-, or polyimide-based film layer substantially cannot be stripped off after the formation thereof (after a thermal cure process has been performed), and therefore needs to be left as a permanent film. Accordingly, various kinds of reliability tests (test on the reliability of adhesion to the wafer, and the like) need to be performed on the wafer to which the permanent film (film layer for warping correction) is attached.
However, in the above described case, there is the following problem: when the wafer is finally diced to be divided into individual semiconductor chips (devices), chipping, cracking, and the like, occur in each chip due to a mechanical shock during the dicing, and thus delamination occurs between the relevant film layer and the chip back surface. Namely, since delamination of the permanent film (film layer) from the chip back surface occurs after various kinds of reliability tests have been performed, it makes no sense that the reliability tests have been performed.